Flat metal features for microelectronics applications

ABSTRACT

Advanced flat metals for microelectronics are provided. While conventional processes create large damascene features that have a dishing defect that causes failure in bonded devices, example systems and methods described herein create large damascene features that are planar. In an implementation, an annealing process creates large grains or large metallic crystals of copper in large damascene cavities, while a thinner layer of copper over the field of a substrate anneals into smaller grains of copper. The large grains of copper in the damascene cavities resist dishing defects during chemical-mechanical planarization (CMP), resulting in very flat damascene features. In an implementation, layers of resist and layers of a second coating material may be applied in various ways to resist dishing during chemical-mechanical planarization (CMP), resulting in very flat damascene features.

RELATED APPLICATION

This patent application is a divisional of and claims priority to U.S. patent application Ser. No. 16/563,512, filed Sep. 6, 2019, which is a divisional of U.S. patent application Ser. No. 15/994,435, filed May 31, 2018, now U.S. Pat. No. 10,446,441, issued Oct. 15, 2019, which claims the benefit of priority to U.S. Provisional Patent Application No. 62/515,410, filed Jun. 5, 2017, which are incorporated herein by reference in their entirety.

BACKGROUND

In the back-end-of-line metallization layers formed during fabrication of integrated circuits, copper is typically used for electrical interconnections. Conductive copper features using a damascene, dual-damascene or via process begin with etching patterns in order to create open trenches, vias, or other cavities where the copper features will be inlayed, in an underlying substrate, such as silicon, silicon oxide, or a low-dielectric-constant (low k dielectric) insulating layer. A barrier/adhesion layer is coated over the etched and patterned substrate, and copper metal is typically deposited on the substrate to overfill the open cavities. A thermal treatment can be performed to stabilize the grain structure of the metal. A chemical-mechanical planarization (CMP) process may then be applied to remove the unwanted metal overburden that extends above the top surface of the substrate. The copper metal, for example, that remains in the substrate becomes the patterned copper conductor for circuits of the integrated circuit.

Successive layers of insulator material and copper can build a multilayered interconnection structure. One or more CMP processes remove the overburden copper and the barrier layer in a planar and uniform manner, ideally stopping at each substrate surface. However, over the patterned copper conductor features, the CMP process may introduce some dishing in larger copper features that have a larger surface area, because the copper is often softer than the dielectric layer, which may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, diamond-like-carbon or the like. The larger the width of the cavity that has been filled with copper metal, for example, the larger the observed dishing during the polishing.

As shown in FIG. 1, dishing 100 is a concave dip defect in the top surface 102 of a metal feature 104, and the dishing 100 becomes more pronounced in relation to the width 106 of the metal feature 104, especially for large damascene features 104 with widths 106 greater than 4 microns (4μ). Typically, the dishing 100 increases with increasing width of the conductive feature 106. The fabrication process begins with a barrier 108 and seed layer 110 deposited in cavities 112 (trenches or vias) of an insulator or semiconductive substrate 114.

The cavities 112 may then be plated with metal to overfill the cavity and cover the surface surrounding the cavity 112, which may be referred to as the “field” to distinguish this surface area from the cavity itself. In one example, for copper deposited from an appropriate conventional copper additive plating bath, a field metal thickness T_(f) 116 and a cavity metal thickness T_(c) 118 are similar in thickness. The field metal thickness T_(f) 116 is typically greater than the overburden metal thickness T_(o) 120 over the cavities 112. After thermal treatment to partially stabilize the grain structure of the metal, the grain size of the metal field metal thickness T_(f) 116 is similar to the grain size of the cavity metal thickness T_(c) 118.

A planarization process, such as a CMP process (illustrated by dashed arrow 122) stops at the barrier layer 108 over the field after polishing with a deformable pad. On account of the similar grain size between the field metal T_(f) 116 and the cavity metal T_(c) 118, the removal rates of the field metal T_(f) 116 and the cavity metal T_(c) 118 are quite similar with a given etchant or polishing slurry.

Then, after removal of the barrier layer 108, the substrate 114 has metal features 104 with the excessive dishing 100. As an example, for a one-micron deep cavity with a width 106 of 4-10 microns, the dishing 100 may vary between 10-50 nm. For larger cavities (in diameter, length, width, etc.) the dishing 100 may readily exceed 30 nm.

When two metal features 104 & 104′ are joined to make a bonded feature 124, such as a conductive connection (with each other) for large pad bonding, the dishing 100 on both surfaces creates an unwanted space 126 between the surfaces of the two metal features 104 & 104′. The unwanted space 126 may be continuous or discontinuous along the width of the cavities in the bonded metal features 104 and 104′. In some examples, the length of the unwanted cavity (dishing) 126 may comprise a dip magnitude that is 5-60% of the width 106 of the width of the metal feature 104 in the dielectric cavity. The dishing 100 and spaces 126 are unacceptable defects in bonded damascene features, and such large defects are a major source of failure in bonded devices.

FIG. 2 shows an example conventional approach for creating bonded features, when dishing is present. In diagram 200, a substrate with a conductive feature with excessive dishing and dielectric erosion has a pad opening dimension P₁. In diagram 202, the substrate has been coated with one or more layers of dielectric material. In diagram 204, the dielectric has been planarized. In diagram 206, lithographic patterning is formed atop the planarized dielectric. In diagram 208, single or dual damascene etching processes form a second pad opening P₂, where P₂ is less than P₁. In diagram 210, a barrier layer and seed layer (not shown) have been placed, and metal deposition has occurred. The plated metal is annealed to partially stabilize the grains of the coated metal. In diagram 212, metal planarization is performed. In diagram 214, two damascene features are bonded after surface preparation and substrate assembly.

The example conventional approach of FIG. 2 has some drawbacks and limitations. First, more than seven additional steps are needed to solve the initial dishing of the large damascene features after CMP. Secondly, the second pad opening P₂ in diagram 212 is always smaller than the first pad opening P₁. Thirdly, this technique, used in some instances when creating direct bond interconnect (DBI®) hybrid bonding layers, can be relatively expensive. Fourth, the example conventional approach results in a loss of wiring freedom or design flexibility in which coplanar large metal and small metal features are components of the bonding surface.

SUMMARY

Advanced flat metals for microelectronics and advanced device packaging are provided. While conventional processes create large damascene features that have a large dishing defect, which causes failure in bonded devices, example systems and methods described herein create large damascene features that are planar. In one example, methods described herein create planar small, medium and large features on a bonding surface. In another example, the method of this invention creates a bonded apparatus wherein the bonded surfaces may comprise small, medium and large damascene cavities. In an implementation, large grains or large metallic crystals are formed in large (T_(c)) damascene cavities and much smaller grains or metallic crystals are formed in thinner (T_(f)) field metal regions. The etching rate or removal rate of the smaller metal grains in the field is higher than those of the large metal grains in the cavity. This differential removal rate between the field metal with thickness T_(f) and cavity metal with larger thickness T, produces slightly domed metal features over damascene cavities. Further polishing of the substrate produces flat metal features over the various damascene cavities. In some embodiments, the metal features are planar in metal widths varying from submicron features to features larger than 30 microns. In other embodiments, the width of the planar cavities exceeds 31 microns, and the related dishing may be less than 10 nm or, in many cases, less than 3 nm.

In various implementations, layers of resist and layers of a second coating material may be applied in various ways to resist dishing during chemical-mechanical planarization (CMP), resulting in very flat damascene features.

This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used as an aid in limiting the scope of the claimed subject matter.

BRIEF DESCRIPTION OF THE DRAWINGS

Certain embodiments of the disclosure will hereafter be described with reference to the accompanying drawings, wherein like reference numerals denote like elements. It should be understood, however, that the accompanying figures illustrate the various implementations described herein and are not meant to limit the scope of various technologies described herein.

FIG. 1 is a diagram of a conventional dishing defect in the top surface of a metal feature.

FIG. 2 is a diagram of a conventional approach for creating bonded damascene features, when dishing defects are conventionally present.

FIG. 3 is a diagram showing an example process for forming a large planar metal feature for microelectronics.

FIG. 4 is a diagram showing continuation steps of the example process of FIG. 3.

FIG. 5 is a diagram showing continuation steps of the example process of FIG. 3.

FIG. 6 is a diagram showing continuation steps of the example process of FIG. 3.

FIG. 7 is a diagram showing example variations of the process shown in FIGS. 3-6.

FIG. 8 is a diagram showing an example technique of masking the field of a substrate while plating a thick seed layer to fill damascene cavities with metal, as a variation when forming metal features with different grain sizes in the cavities versus the field, prior to performing CMP.

FIG. 9 is a diagram showing an example technique of masking the field of a substrate while plating a thick seed layer to fill damascene cavities with metal to make the plated metal surface of the cavity layer higher than the surface of the field of the substrate, as a variation when forming metal features with different grain sizes in the cavities versus the field, prior to performing CMP.

FIG. 10 is a diagram showing an example variation of the example process that includes selectively masking the metal fill over the damascene cavities to minimize dishing during planarization, as a variation when forming metal features with different grain sizes in the cavities versus the field, prior to performing CMP.

FIG. 11 is a diagram showing an example variation of the example process that includes thinning a field metal thickness before annealing, as a variation when forming metal features with different grain sizes in the cavities versus the field, prior to performing CMP.

FIG. 12 is a diagram showing an example variation of the example process of storing a substrate at a low temperature before thinning a field metal thickness, and then annealing at temperature to form different grain sizes in the open cavities versus the field of the substrate, prior to CMP.

FIG. 13 is a diagram showing another example method of creating planar large damascene metal features, using selective coating on surfaces of the features to resist planarization forces that cause the dishing defect.

FIG. 14 is a diagram showing an example variation of the example method of FIG. 13 of selectively coating the surface of the damascene features to resist planarization forces that cause dishing defects.

FIG. 15 is a flow diagram of an example method of creating large flat conductive features.

FIG. 16 is a flow diagram of an example continuation method of the example method shown in FIG. 15.

DETAILED DESCRIPTION Overview

This disclosure describes advanced flat metals for microelectronics and packaging applications. While conventional processes create large damascene features that have high dishing defects that can cause failure in bonded devices, example systems and methods described herein create large damascene features that are planar or substantially planar. In an implementation, after depositing metal within large cavities of a substrate, the metal is formed in such a manner that the metal is vertically thicker within the cavity than the metal on the surrounding field portion of the substrate nearby the cavities. An annealing process is applied, for example at approximately 25-150° C., which creates large metal grains and large metallic crystals of the metal, such as copper, within the larger cavities, and creates smaller metal grains and smaller metallic crystals of the copper on the thinner field portion of the substrate. The polishing rate and removal rate of the smaller metal grains in the field is higher than the polishing and removal rates of the large metal grains within the cavities. This differential removal rate between the field metal and the cavity metal produces slightly domed metal features over damascene cavities. Further polishing down to the substrate can produce flat metal features over the various large damascene cavities. In some embodiments, the polished metal features have widths varying from the submicron range to metal features spanning cavities larger than 10 microns. In other embodiments, the width of the planar metal features spanning cavities exceeds 40 microns, and the related dishing is less than 10 nm, or sometimes even less than 3 nm, across the surface of the metal feature. The relatively large grains of copper within the damascene cavities have lower removal rates than the smaller copper grains in the field during chemical-mechanical planarization (CMP), resulting in very flat features across a die or across the surface of the planarized substrate.

In an implementation, layers of resist and layers of a second coating material may be applied in various ways to further resist dishing defects during chemical-mechanical planarization (CMP), resulting in very flat damascene metal features.

Achievement of the advanced flat metals described herein can extend the range of DBI® hybrid bonding processes (Invensas Bonding Technologies, Inc., San Jose, Calif.) to large metal features of 10-1000 μm size, for example. DBI® hybrid bonding is a low temperature direct bonding technology that allows wafer-to-wafer and die-to-wafer bonding with typically fine-pitch 3D electrical interconnects. The wafers or die surfaces are planarized and bond pads can be flat or slightly recessed in a dielectric layer. The wafers or die are then aligned and bonded at room temperature. The metal interconnects may be formed or improved during a subsequent higher temperature annealing step. The advanced flat metals described herein can also allow formation of the direct bond interface hybrid bonds at even lower temperatures than low temperatures used conventionally.

Example Systems and Processes

FIG. 3 shows an example process for forming a large flat metal feature for microelectronics. In general, the example process includes creating a pattern of cavities for metal features on a substrate of a microelectronic device, forming a metal layer on the patterned substrate, wherein the metal in the cavities is thicker than the metal coating at the field of the substrate, and then annealing the substrate and/or the metal at a temperature, for example, in the range of temperatures between 25-350° C. for a period of time varying between 30 seconds to 48 hours. For example, the variables may depend on the plating bath additives and the concentration of impurities in the plated metal. The lower the impurity concentration in the plated metal, the lower the needed annealing temperature. Annealing at lower temperatures may be performed at a temperature in a range from room temperature to 100° C., for about 60 minutes, but in some circumstances from 4-48 hours. Similarly, the thicker the plated metal over the cavity, the lower the preferred annealing temperature. The annealing process generates metal grains of different sizes, with the sizes of the metal grains related to a thickness or a depth of the metal at each location on the substrate, including over the damascene cavities. In some examples, a higher temperature process may be utilized for a relatively shorter duration or, conversely, a lower temperature process may be utilized for a relatively longer length of time. The cavities formed have relatively large metal grains, while the metal coating on the field of the substrate has relatively small metal grains as compared to the grains in the cavity. In an implementation, a width of the grain size of a conductor within the conductive layer-filled cavity is more than 5% of the width of a cavity containing the metal feature.

The metal is then planarized. The relatively larger metal grains in the cavity undergo removal more slowly than the relatively smaller metal grains of the field, forming a slightly raised or domed surface over the cavities. Further polishing results in a substantially flat metal feature. By controlling these various aspects, flat metal features are achieved without having a significant dishing defect from the planarization stages.

FIG. 3 further illustrates an implementation in which a barrier layer and a first seed layer are first deposited in a preformed cavity and on the field. The example process then includes depositing the metal on the first seed layer to partially fill the cavity and cover the field of the substrate with the metal, wherein the field layer of the metal has a depth of less than 0.6 microns and preferably less than 0.3 microns. Resist masking is selectively applied over the field portion of the substrate. Additional metal is deposited in the cavity to create a cavity layer of the metal thicker than the field layer of the metal. The resist masking is then cleaned or removed. It is of note that the thickness of the metal in the cavity T_(c) is substantially larger than the thickness of the metal in the field T_(f). In some embodiments, the depth of the cavity may vary between 1 to 7 microns or even higher and the ratio of metal thickness in the cavity (T_(c)) to that of the field metal (T_(f)) is at least 1.5 to 12 or even higher. The example process then includes thermally annealing the metal coated substrate at temperatures between 25-350° C. for times varying between 30 seconds up to 48 hours to form larger metal grains in the cavity and smaller metal grains in the field portion of the substrate. A chemical-mechanical planarization (CMP) process is performed on the substrate to remove material down to the barrier layer. Then, the barrier/adhesion layer covering the field is removed. While the process may be described with regard to one cavity, it should be appreciated that the technique can be expanded for multiple cavities of varying size across a given substrate. The cavity(ies) may have any of a number of shapes including round, square, polygonal, elongated, linear, or other suitable feature shape as needed for a given application.

FIG. 3, diagram 300 shows a barrier layer 302 and seed layer 304 coating placed in a large damascene cavity 306 in a substrate 308. In diagram 310, metal 312 is deposited over the substrate 308 to at least partially fill the large damascene cavity 306. The thickness of metal deposited on the field of the substrate may be less than 0.6 microns, and preferably less than 0.3 microns, for example.

In diagram 314, a resist masking 316 is selectively applied on the top surface of the metal 312 on the field of the substrate. In diagram 314, the thickness of the field metal 318 (e.g., less than 0.6μ) is less than the thickness of the cavity metal 322, to be placed in diagram 320. In diagram 320, additional metal 324 is plated or deposited in the unmasked large cavities, to form a thicker metal deposit 322 in the cavities, further assuring that the cavity metal 322 is thicker than the field metal 318. In diagram 326, the resist masking 316 is then cleaned off

In diagram 328, an annealing process is applied, preferably at temperatures between 25-200° C. for times varying between 10 minutes to 2-12 hours, forming relatively smaller grains 330 of the metal in the thinner layer of the field metal 318, and forming relatively larger grains 332 of the metal in the thicker cavity metal layer 322.

In some applications after the metal coating step of diagram 320, the plated substrate may be annealed with the resist layer 316 if the annealing temperature is kept below 150° C., for example. A CMP method is then used to remove the resist layer 316 and the unwanted metal overburden in the field T_(f).

In diagram 334, the large grains 332 of metal in the thicker cavity layer 322 resist an intermediate CMP process more than the smaller grains 330 of the metal in the thinner field layer 318, leaving a dome or raised surface 336 over the cavities. In diagram 338, the conductive metal is planarized, stopping at the barrier layer 302. In diagram 340, the barrier layer 302 is removed leaving a large planar damascene pad 342 or conductive feature, having a span of 10μ, or more, for example.

In FIG. 4, at diagram 400, the surfaces of the substrate 402 with a large metal pad 404 or, in diagram 406, a substrate 402 with multiple large pads 408 & 410 are processed for bonding. Diagrams 412 and 414 depict assembled and bonded substrates 402 & 402′, from the substrates that have one or more of the large conductive features in diagrams 400 and 406. In some of these embodiments, the DBI® hybrid bonding layer is freed from conventional limitations. When a DBI® hybrid bonding layer is conventionally used (for example, referring to FIG. 2), the pad P₂ is conventionally limited to being smaller than the width of the pad P₁ beneath, as in diagram 212. But the example methods and structures described herein enable elimination of such DBI® hybrid bonding layer limitations from the structure of the substrates, so that the top bonding pad 416 or via may be the same area as the pad 418 beneath.

In FIG. 5, diagram 500 shows embodiments in which the polished metal features 502 & 504 & 506 bond with other instances of the polished metal features on substrates being bonded together. The polished metal features 502 & 504 & 506, as from the polish stage 340 shown in FIG. 3, have widths varying from submicron scale to cavities larger than 30 microns.

In one embodiment, the width of one of the metal filled cavities of the bonded apparatus in FIG. 5 is more than 2 to 5 times the width of another metal filled cavity in the apparatus.

In other embodiments, the width of the planar cavities may exceed 40 microns, but the related dishing is less than 3 nm and less than 10 nm total across the surface of a die on the substrate or across the surface of the planarized substrate 402. The planarized substrates 402 & 402′ with conductive features 504′ & 506′ & 508′ of varying widths made possible by the example methods described herein are further processed. This may include activating the surface of the dielectric layer, and also the metallic layer in some instances, then assembling face-to-face and contact-bonding together. In some applications, both corresponding and non-corresponding large metal cavities with their metal features are aligned and bonded, such as large metal features 508 & 510 to smaller metal features 504, and smaller metal features 514 & 516 & 518 & 520 to larger metal feature 512. One or more traces, trenches, or vias may be bonded to larger conductive pads, enabled and facilitated by the highly planar surfaces of the metal features afforded by the example processes described herein.

FIG. 6 shows one or more smaller dies 602 & 604 & 606 comprised of pads, trenches, vias of various sizes bonded to a larger substrate 608 comprised of pads, trenches and vias of various sizes. In some applications, the width of the vias, trenches or pads on the bonding surfaces of substrate 608 and dies 602, 604 and 606 may be between approximately 0.5-100 microns. Thus, the width of a conductive layer in a portion of the bonding surface of the substrate or the dies may be more than 30% the width of another conductive layer disposed on the bonding surfaces.

In the case of the sizes of the dies, the larger substrate 608 of two bonded dies or substrates may be larger than the smaller die 606 by more than 30% and die 606 may larger than die 604 by more than 50%, for example. In some embodiments, the electrical conductive layer or pad on example die 602 may be smaller than the electrical conductive layer or pad on die 604. Also, multiple dies of various thicknesses may be directly bonded to the larger substrate 608. For example, die 602 may be more than 20% thicker than die 604. Similarly substrate 608 may be thicker or thinner than one of the dies directly bonded to it.

In an implementation, a first surface of a first substrate is bonded to a first surface of a second substrate. The first bonding surface of the first substrate is a conductive layer-filled cavity, the cavity having a width of at least 5 microns. A first bonding surface of the second substrate has one or more conductive layer-filled cavities, wherein a width of a grain size of a conductor within a conductive layer-filled cavity is more than 5% of the width of a cavity in the first or second substrate.

Smaller bonded substrates may be microprocessors, memory devices, passive devices, optical devices, mechanical devices, MEMS devices, frequency filters, and/or a direct band gap device, and combinations of these and other devices. In other applications, the back side of a first bonded die or substrate may be processed for subsequent bonding of one or more active devices, passive devices, optical devices, or MEMS devices, as described above. The pads are shown grossly exaggerated to highlight the contact structures; typically, the electrical conductive layers or structures are far smaller in relation to the associated die.

FIG. 7 shows example variations of the process shown in FIGS. 3-6. In diagram 700, depositing the additional metal in the large cavities includes creating a cavity layer 702 of the metal and a field layer 704 of the metal that have coplanar top surfaces, and the cavity layer 702 of the metal is thicker than the field layer 704 of the metal. In diagram 706, depositing the additional metal in the cavities includes creating a cavity layer 708 of the metal and a field layer 710 of the metal with non-coplanar top surfaces, wherein the surface of the cavity layer 708 is flat and is higher than the surface of the field layer 710. Alternatively, in diagram 712, depositing the additional metal in the cavities includes creating a cavity layer 714 of the metal and a field layer 716 of the metal with non-coplanar top surfaces, wherein the surface of the cavity layer 714 is non-flat, such as domed, and is mostly higher than the surface of the field layer 716.

FIG. 8 shows another example technique for making relatively large flat metal features, with little or no dipping. A substrate 800 is coated with a barrier layer 802 and a metallic seed layer 804, in cavities 806, such as damascene cavities, of the substrate 800 and on a field 808 of the substrate 800. A mask 810 is applied to the field 808 of the substrate 800. The substrate is plated with metal layer 812 to fill the seeded cavity 806.

The resist masking 810 is then removed 814 from the field layer 808. Then, additional metal 816 is deposited over the surface of the substrate 800 without the resist layer to form the new structure 816 with field thickness 820 and corresponding cavity metal 818 and the thickness of metal in the cavity T_(CU) is substantially thicker than the thickness of the metal in the field T_(f). The process proceeds with thermally annealing 822 the substrate and layers, to make small grained metal 824 crystals over the field 808, and large grained metal crystals 826 in the cavities 806. An intermediate chemical-mechanical planarization (CMP) process 828 is applied on the cavity layer 818 of the metal and the field layer 820 of the metal.

The cavity layer 818 of the metal is then planarized 830 down to the barrier layer 802 covering the field 808. The barrier layer 802 is then removed from the field 808, leaving the large metal damascene features 832 with a high degree of flatness, and with little or no dipping.

FIG. 9 shows another alternative process for making large flat damascene features. A substrate 900 is coated with a barrier layer 902 and a metallic seed layer 904, in cavities 906, such as damascene cavities, of the substrate 900 and on a field 908 of the substrate 900. A mask 910 is applied to the field 908 of the substrate 900. A second seed layer may then be applied in the cavities 906, the second seed layer having a thickness of at least 50 nm, for example. The first seed layer 904, or the second seed layer in the cavity 906, as applicable, is then plated or deposited with metal 912 to fill the damascene cavities 906, for forming metal features that have different grain sizes in the cavities 906 than on the fields 908 of the substrate 900, prior to performing CMP. The deposited metal 912 has a thickness 914 that makes the top surface 916 of the deposited metal 912 higher than the top surface of the seed layer 904 under the resist masking material 910.

At 918, the resist masking 910 is then removed from the seed layer 904 of the metal on the field 908 of the substrate 900. At this point, the cavity layer 914 of the metal is thicker than the field layer 918 of the metal.

In some applications the substrate may be annealed with the resist layer 910 over the substrate prior to the removal of the resist layer 910 and the unwanted field metals by CMP methods.

At 920, the process proceeds with thermally annealing the substrate and layers, to make small crystals 922 of grained metal over the field 908, and large crystals 924 of grained metal in the cavities 906.

At 926, an intermediate chemical-mechanical planarization (CMP) process 928 is applied on the cavity layer 914 of the metal and the field layer 918 of the metal.

At 930, the cavity layer 914 of the metal is then planarized 932 down to the barrier layer 902 covering the field 908.

At 934, the barrier layer 902 is then removed from the field 908, leaving the large metal damascene features 934 with a high degree of flatness, and with little or no dipping.

FIG. 10 shows another alternative process for fabricating large flat damascene features. A substrate 1000 is coated with a barrier layer 1002 and a seed layer 1004 for depositing metal. A metal fill is deposited or plated on the seed layer 1004, both in cavities 1006 of the substrate 1000 and on the surrounding fields 1008 of the substrate 1000. A cavity layer 1010 of the metal has approximately the same thickness as a field layer 1012 of the metal, but with the field layer 1012 having a greater thickness than an overburden part 1014 over the cavity layer 1010 over the cavities 1006.

At 1016, the top surface of the cavity layer 1010 is selectively covered with a masking material 1018.

At 1020, the field layer 1012 of the metal is etched, so that a thickness of the cavity layer 1010 is now greater than a thickness of the field layer 1012′ of the metal.

At 1022, thermal annealing of the metal creates large grains 1024 of the metal in the cavity layer 1010 of the metal and relatively small grains 1026 of the metal in the field layer 1012′ of the metal.

At 1028, the cavity layer 1010 of the metal is planarized 1030 down to the barrier layer 1002 covering the field 1008. The barrier layer 1002 is then removed from the field 1008, leaving large flat metal damascene features with a high degree of flatness and little or no dipping.

FIG. 11 shows another example process that includes thinning a field metal thickness before annealing, as a variation to the previous methods described above.

Starting with a substrate 1100, the example process includes depositing a barrier layer 1102 and a first seed layer 1104 in the cavities 1106 and on the field 1108 of the substrate 1100.

A metal is deposited on the seed layer 1104 in the cavities 1106 and on the fields 1108, creating a cavity layer 1110 of metal that is approximately the same thickness as the field layer 1112 of metal, with the field layer 1112 having a greater thickness than an overburden part 1114 of the cavity layer 1110.

At 1116, the example process includes planarizing 1118 the cavity layer 1110 and the field layer 1112 to a substantially coplanar surface, so that the planarized field layer 1112′ has a thickness approximately equal to the overburden part 1114 of the cavity layer 1110, and the field thickness is substantially thinner than the thickness of the metal in the cavity layer 1110. In this embodiment, the key requirement after the first metal removal or forming step is that the thickness of the metal within the cavity T_(c) is substantially higher than the thickness of the metal in the field T_(f).

At 1120, the example process includes thermally annealing the metal to create large grains 1122 of the metal in the cavity layer 1110 of the metal and small grains 1124 of the metal in the field layer 1112′ of the metal.

At 1126, the cavity layer 1110 of the metal is planarized down 1128 to the barrier layer 1102 covering the field. The barrier layer 1102 is then removed from the field 1108, leaving large area metal damascene features 1130 with a high degree of flatness, and little or no dipping of the top surfaces. In some applications the width of one or more of the large grains in the cavity 1106 is more than 3% of the width the cavity and is more than 10% in other embodiments.

FIG. 12 shows a variation of the example process for making large flat metal features. A substrate is coated with a barrier layer 1202 and optionally a seed layer 1204, and a metal 1206 is plated or deposited in the cavities 1208 and on the fields 1210 of the substrate 1200. A cavity layer 1212 of the metal has a thickness approximately the same thickness as a field layer 1214 of the metal, and the field layer 1214 has a greater thickness than an overburden part 1216 of the cavity layer 1212 of the metal.

At 1218, the example process includes storing the plated substrate 1200 at a low temperature, for example at a temperature of 10° C. or lower, to preserve the submicron grain size of the plated metal 1206. The lowered temperature also suppresses undesirable grain growth in the plated metal 1206 at room temperature, before thinning the plated metal 1206.

At 1220, the top of the cooled field layer 1214 of metal and the cooled cavity layer 1212 of metal are planarized 1222 preferably at the low temperature for example below 20° C. In one embodiment, the planarized field layer 1214′ has a thickness equal to or approximately equal to an overburden part 1216 over the cavity layer 1212 of metal over the cavities 1208. It is preferable that the thickness of the metal in the field 1214 be less than 600 nm and less than 300 nm before the annealing step. Also, in some embodiments, the thickness of the metal over the barrier layer within the cavity may be more than 3 to 50 times the thickness of the planarized field metal 1228.

At 1224, the metal 1206 now planarized, is thermally annealed to create large grains 1226 of the metal in the cavity layer 1212 of the metal and small grains 1228 of the metal in the planarized field layer 1214′ of the metal.

At 1230, the cavity layer 1212 of the metal is planarized 1232 down to the barrier layer 1202 covering the field 1210. The barrier layer 1202 is then removed from the fields 1210, leaving the large metal features 1234 that have a high degree of flatness, with little or no dipping across their top surfaces.

FIG. 13 shows another example method of creating planar large damascene metal features. The example method of FIG. 13 prevents dishing of the large metal features by selectively coating the surface of the features to resist planarization forces that cause the dishing defect. The example process of FIG. 13 may be used alone, or in conjunction with the formation of large metal grains that resist dishing, as in the methods described above.

Starting with a substrate 1300, the example method begins with creating trenches or cavities 1302 for the metal features in the substrate 1300. A barrier layer 1304 and a first seed layer 1306 are deposited in the cavities 1302 and on fields 1308 of the substrate.

At 1310, a metal 1312 is deposited, for example on a seed layer in the cavities 1302, and on the fields 1308 to make a cavity layer 1314 of metal filling the cavities 1302, the cavity layer 1314 approximately the same thickness as the field layers 1316, and the field layer 1316 having a greater thickness than an overburden part 1318 of the cavity layer 1314.

At 1320, a resist masking layer 1322 is applied over the field layers 1316 but not over the cavity layer 1314.

At 1324, the example method continues with selectively applying a coating of a material 1326 over the cavity layer 1314 of metal. The coating 1326 may be an electrolytic material, a spin-on dielectric material, or an electrolessly coated layer, for example.

Next, at 1328, the resist masking 1322 is cleaned from the field layer 1316 of metal.

At 1330, the cavity layer 1314 of the metal and the field layer 1316 of metal are planarized 1332, leaving large flat metal damascene features 1334. The planarization 1332 may be a chemical-mechanical planarization (CMP) process over the cavity layer 1314 and the field layer 1316 of the metal that achieves the flat conductive metal features 1334. The coating 1326 on the cavity layer 1314 protects the cavity layer 1314 at least in part from the CMP process 1332 and prevents a dishing of the cavity layer 1314 while the CMP process 1332 removes the field layer 1316.

In an implementation, selectively applying a coating 1326 of material over the cavity layer 1314 includes selectively applying the coating 1326 over the cavity layer 1314 and on sidewalls 1336 of the field layer 1316 adjacent to the cavity layer 1314 but not over the resist masking layer 1322 over the field layer 1316.

FIG. 14 shows a variation of the example method of FIG. 13, which describes selectively coating the surface of the damascene features to resist planarization forces that cause the dishing defect on large metal features.

At 1400, an etched substrate 1402 is plated with metal 1404 and planarized to obtain a substantially planar surface 1406 over both the cavities 1408 and fields 1410 of the substrate 1402.

On the planar surface 1406, resist masking 1412 is placed over the fields 1410 of the substrate. A coating 1414 of a material is also selectively applied over the unmasked cavity layer 1416 but not over the resist masking layer 1412.

At 1418, the resist masking 1412 is removed, and the material coating 1414 is planarized 1420 to provide large damascene metal features 1422 that have a high degree of flatness, with little or no dipping across the top surface of the large metal features 1422.

The large planar metal features 1422 with little or no dipping across the top surfaces can be bonded together 1424 from different substrates, providing a substantial improvement over conventional limitations, such as that in diagram 212 (FIG. 2), where dimension P₂ of a bonding surface made by conventional damascene methods applied to a die or substrate is necessarily less than dimension P₁ of the conventional die or substrate. At example bonding interface 1424 (FIG. 14), the dimension of the bonding surface P₂ can be equal to (1424) or greater than (1426) dimension P₁. This provides example structures, such as large metal bonding interface 1428, that are not possible to produce, or not possible to easily produce conventionally without numerous extra steps that would make such a process conventionally unfeasible.

Thus, the bonding surface of structure 212 conventionally comprises a second pad with a dimension P₂ smaller than the width of the first pad P₁ beneath. This conventional approach results in a loss of wiring freedom or design flexibility, limiting the use of coplanar large metal and small metal features and components in the bonding surface. The example methods described herein eliminate the restrictions of a smaller planar second pad overlaying a larger first pad, as imposed by the prior art.

The example methods may be applied to form a bonding surface in which a width of the second pad P₂ is larger than the width of the first pad P₁ beneath. In an embodiment, the width of one of the second pads may be 2-50 times larger than the width of the metal layer beneath. For bonding operations, one or more of the cleaned planarized surfaces may be activated in a gentle nitrogen, boron, or fluoride plasma ambient or combinations thereof. The clean prepared surfaces are assembled with intimate contact and can be bonded by further thermal treatment of the coupled substrates.

In an implementation, and example apparatus has a first substrate beneath a second substrate, a bonding surface of the first substrate bonded to a bonding surface of the second substrate, and the bonding surface of the first substrate has conductive layer-filled cavities. A conductive layer-filled cavity of the bonding surface of the first substrate has a width of at least 5 microns, and the bonding surface of the second substrate also has conductive layer-filled cavities. A width of a conductive layer-filled cavity of the bonding surface of the second substrate is 2-20 times larger, for example, than a width of a conductive layer-filled cavity of the first substrate beneath the bonding surface of the second substrate.

Referring back through FIGS. 3-15, in some applications, the barrier layer may serve as the seed layer. While in other applications, the seed layer and the plated material comprise similar materials.

FIG. 15 shows an example method 1500 of creating large flat damascene conductive features. In the flow diagram, operations of the example method 1500 are shown in discreet blocks.

At block 1502, a pattern of damascene cavities for metal features is etched or formed in or on a substrate for a microelectronic device.

At block 1504, the substrate and the pattern are coated with a deposited metal, wherein the metal within the pattern of the damascene cavities has a greater thickness than the thickness of the metal on the field of the substrate.

At block 1506, the metal is annealed to generate metal grains of different sizes, the sizes of the metal grains related to a thickness or a depth of the metal at each location over the un-etched substrate and over the etched pattern of damascene cavities, the metal in the pattern of damascene cavities annealing to relatively large metal grains and the metal that is coating the fields of the substrate annealing to relatively small metal grains.

At block 1508, the metal is planarized, wherein the large metal grains in the pattern of damascene cavities planarize to flat metal features with a minimum dishing defect from the planarization.

The example method 1500 may end at block 1508, with the flat metal features planarized with a minimum dishing defect. Variations of this example method, and other processes useful for forming the large flat metal features, are also shown in FIGS. 2-14.

FIG. 16 shows optional continuation steps 1600 of the example method 1500, for further processing.

At block 1602 the surface of the planar substrates with flat metal features are processed for bonding.

At block 1604 the processed surface of the substrate is aligned and bonded face-to-face with another instance of a processed surface of another substrate that has flat metal features, at room temperature or at low temperatures.

At block 1606 the bonded substrates are thermally exposed to a higher temperature in order for the opposing conductive layers of the opposing flat metal features to fuse together permanently.

At block 1608, a backside of the first bonded substrate is processed for bonding with another additional substrate.

In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols have been set forth to provide a thorough understanding of the disclosed embodiments. In some instances, the terminology and symbols may imply specific details that are not required to practice those embodiments. For example, any of the specific dimensions, quantities, material types, fabrication steps and the like can be different from those described above in alternative embodiments. The term “coupled” is used herein to express a direct connection as well as a connection through one or more intervening circuits or structures. The terms “example,” “embodiment,” and “implementation” are used to express an example, not a preference or requirement. Also, the terms “may” and “can” are used interchangeably to denote optional (permissible) subject matter. The absence of either term should not be construed as meaning that a given feature or technique is required.

Various modifications and changes can be made to the embodiments presented herein without departing from the broader spirit and scope of the disclosure. For example, features or aspects of any of the embodiments can be applied in combination with any other of the embodiments or in place of counterpart features or aspects thereof. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

While the present disclosure has been disclosed with respect to a limited number of embodiments, those skilled in the art, having the benefit of this disclosure, will appreciate numerous modifications and variations possible given the description. It is intended that the appended claims cover such modifications and variations as fall within the true spirit and scope of the disclosure. 

1. An apparatus comprising: a first substrate comprising a first bonding surface that comprises a first conductive layer-filled cavity, the first conductive layer-filled cavity having a width of at least 5 microns; and a second substrate comprising a second bonding surface that comprises a second conductive layer-filled cavity, wherein a width of a grain size of a conductor within the second conductive layer-filled cavity is more than 5% of the width of one of (i) the first conductive layer-filled cavity or (ii) the second conductive layer-filled cavity wherein the first bonding surface is bonded to the second bonding surface.
 2. The apparatus of claim 1, further comprising: a first barrier layer over a surface of the first conductive layer-filled cavity; and a second barrier layer over a surface of the second conductive layer-filled cavity.
 3. The apparatus of claim 1, wherein: the first bonding surface comprises one of a nitrogen atomic species, a fluoride atomic species, or a boron atomic species; and the second bonding surface comprises one of a nitrogen atomic species, a fluoride atomic species, or a boron atomic species.
 4. The apparatus of claim 1, wherein a depth of the first conductive layer-filled cavity is between about 1 to 7 microns and a depth of the first conductive layer-filled cavity is between about 1 to about 7 microns.
 5. The apparatus of claim 1, wherein the first bonding surface is bonded to the second bonding surface via a direct bond interface (DBI).
 6. The apparatus of claim 1, wherein the width of the first conductive layer-filled cavity is 2 to 5 times a width of the second conductive layer-filled cavity.
 7. The apparatus of claim 1, wherein: the first bonding surface comprise a first flat conductive metal feature having a width of at least 5 microns on the first substrate, wherein a dishing concavity across the width of the first flat conductive metal feature has a maximum dishing depth of less than 10 nanometers for each micron (nm/μ) of depth of the first flat conductive metal feature; and the second bonding surface comprise a second flat conductive metal feature having a width of at least 5 microns on the second substrate, wherein a dishing concavity across the width of the second flat conductive metal feature has a maximum dishing depth of less than 10 nanometers for each micron (nm/μ) of depth of the second flat conductive metal feature.
 8. The apparatus of claim 7, wherein the first flat conductive metal feature and the second flat conductive metal feature are from a group consisting of: a flat conductive metal feature with a width of at least 10 microns (μm) and a maximum dishing of less than 10 nanometers (nm); a flat conductive metal feature with a width of at least 10 μm and a maximum dishing of less than 10 nanometers per micron (nm/μm) of depth of the flat conductive metal feature; and a bonded metallic feature larger than 10 μm.
 9. The apparatus of claim 7, wherein the width of the first flat conductive metal feature and the width the second flat conductive metal feature are more than 25 microns and the dishing concavity of the first flat conductive metal feature and the second flat conductive metal feature are each less than 10 nanometers.
 10. The apparatus of claim 7, wherein the width of the first flat conductive metal feature and the width of the second flat conductive metal feature are each between 26-150 microns and the dishing concavity of the first flat conductive metal feature and the width of the second flat conductive metal feature are each less than 20 nanometers.
 11. The apparatus of claim 1, wherein at least one of the first substrate or the second substrate comprise a microelectronic device.
 12. An apparatus comprising: a substrate; and a flat conductive metal feature having a width of at least 10 microns on the substrate, wherein a dishing concavity across a width of the flat conductive metal feature has a maximum dishing depth of less than 10 nanometers for each micron (nm/μ) of depth of the flat conductive metal feature.
 13. The apparatus of claim 12, wherein the flat conductive metal feature is from a group consisting of: a flat conductive metal feature with a width of at least 10 microns (pin) and a maximum dishing of less than 10 nanometers (nm); a flat conductive metal feature with a width of at least 10 pin and a maximum dishing of less than 10 nanometers per micron (nm/μm) of depth of the flat conductive metal feature; and a bonded metallic feature larger than 10 μm.
 14. The apparatus of claim 12, wherein the width of the flat conductive metal feature is more than 25 microns and the dishing concavity of the flat conductive metal feature is less than 10 nanometers.
 15. The apparatus of claim 12, wherein the width of the flat conductive metal feature is between 26-150 microns and the dishing concavity of the flat conductive metal feature is less than 20 nanometers.
 16. The apparatus of claim 12, wherein the substrate comprises at least a portion of a microelectronic device.
 17. An apparatus comprising: a first substrate comprising a first bonding surface that comprises a first conductive layer-filled cavity, wherein a conductive layer of the first conductive layer-filled cavity has a width of at least 10 microns; and a second substrate comprising a second bonding surface that comprises a second conductive layer-filled cavity, wherein a width of a conductive layer of the second conductive layer-filled cavity is 2-10 times the width of the conductive layer of the first conductive layer-filled cavity, wherein the first bonding surface is bonded to the second bonding surface.
 18. The apparatus of 17, further comprising: a first barrier layer over a surface of the first conductive layer-filled cavity; and a second barrier layer over a surface of the second conductive layer-filled cavity.
 19. The apparatus of 17, wherein: the first bonding surface comprises one of a nitrogen atomic species, a fluoride atomic species, or a boron atomic species; and the second bonding surface comprises one of a nitrogen atomic species, a fluoride atomic species, or a boron atomic species.
 20. The apparatus of claim 17, wherein at least one of the first substrate or the second substrate comprise a microelectronic device. 